Error correcting method and apparatus

ABSTRACT

A decoding method for digital data having a two-dimensional arrangement including error correction check codes in both for first and second directions, wherein, an error correcting method having a value in which the result of the arithmetic operation for error correction was added to syndromes in at least one of the first and second directions is obtained and error correction is again executed on the basis of this value. In addition, an error correcting apparatus having a plurality of syndrome calculating units are provided so that a plurality of syndromes can be simultaneously calculated.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an error correcting apparatus and, moreparticularly, to method and apparatus for correcting errors in data towhich an error correction code was added.

2. Related Background Art

Hitherto, a product code has been known as a form of an error correctioncode having a two-dimensional arrangement. FIG. 3 is an arrangementdiagram of a product code. In the diagram, the portion of k₁ ×k₂corresponds to the original digital information having a two-dimensionalarrangement. A predetermined check code m₁ is added to every row in a k₁direction shown by an arrow A and a code c_(l) is constructed. On theother hand, a predetermined check code m₂ is added to every column in ak₂ direction shown by an arrow B and a code c₂ is constructed. The codec₁ is the (n₁, k₁) code and the code c₂ is the (n₂, k₂) code.

A sole decoding method in the lateral or vertical direction will befirst described as a decoding method of such a code. The errorcorrection decoding method generally includes the following four steps.

step (1) Syndrome calculation

step (2) Calculation of the error position polynomial and errorevaluation polynomial

step (3) Estimation of the error position and error value (size) inaccordance with the results of the calculation in step 2

step (4) Execution of the error correction of the estimated position andsize

In step (1), since syndromes are obtained as values of the polynomial ofthe (n-1) order in which all of the symbols of the number correspondingto a code length n of the code are used as coefficients, the arithmeticoperation to sequentially input all of the symbols is executed.Therefore, n/S clocks are necessary when the calculation is executed Stimes in parallel for at least one syndrome. On the other hand, in manycases, S is generally set to 1 to reduce the circuit scale. In thiscase, the period of time corresponding to n clocks is necessary. Withrespect to steps (2) to (4) as well, in many cases, the processes aregenerally executed within the period of time of n clocks.

On the other hand, in the case of the product code construction, aseries of error corrections are once executed with respect to the codewords of, for instance, n₂ (=k₂ +m₂) rows in the A direction and aseries of error corrections.are once performed with regard to the codewords of k₁ columns in the B direction. Due to this, the errorcorrecting capability can be raised as compared with the case of, forinstance, the construction in only the A direction.

Further, there has been known a repetitive decoding method whereby theerror corrections in both of the A and B directions as mentioned aboveare further repetitively executed to the codes of the product codeconstruction. According to such a method, the error correctingcapability can be further raised as compared with the case where theerror corrections in the A and B directions are executed once at a timeas mentioned above.

However, in the conventional repetitive method, the above steps (1) to(4) are repeated with respect to each of the code words (there are n₂code words having the arrangement in the A direction and there are n₁code words having the arrangement in the B direction).

Therefore, assuming that the processes are repetitively executed t timesfor the period of time of n clocks in step (1) and for the period oftime of n clocks in steps (2) to (4), the following processing time isneeded.

    {(n.sub.1 +n.sub.1)n.sub.2 +(n.sub.2 +n.sub.2)k.sub.1 }×t=2t(n.sub.1 n.sub.2 +n.sub.2 k.sub.1)                                 (1)

As mentioned above, an extremely long processing time is necessary inthe case of executing the repetitive method as mentioned above in orderto raise the error correcting capability in the conventional manner.

On the other hand, in any of the A and B directions shown in FIG. 3, inthe case of calculating the syndromes, in addition to the problem in theabove repetitive method, there is also a problem such that the datashown in FIG. 3 needs to be read out a plurality of times and it isdifficult to realize the high speed error correcting operation.

The above problems will now be described with reference to FIGS. 4 and5.

FIG. 4 is a diagram showing an example of a conventional error detectioncorrection decoding unit.

In FIG. 4, an explanation will be made with respect to the example ofthe (n-k-2) correction decoding of the data which was double encoded bythe code lengths (n₁, k₁) and (n₂, k₂) in the C₁ (lateral) and C₂(vertical) directions as shown in FIG. 5. The data block including theerror correction code (ECC) shown in FIG. 5 is hereinafter referred toas an ECC block.

In the construction shown in FIG. 5, the data to which errors were mixedby the transmission path is first written into a data memory 301comprising a RAM on a unit basis of n₁ ×n₂ blocks After that, the datais sequentially read out in the C₁ direction by the address operation ofthe memory 301 and syndromes are calculated by a syndrome calculatingunit 302. The error position and size are calculated by an errordetection correction processing unit 303 on the basis of the syndromescalculated, thereby correcting the erroneous data in the data memory301. After such processes were executed with respect to n₁ lines, thesimilar processes are also executed in the C₂ direction with regard ton₂ lines. After completion of a series of processes, the error correcteddata is read out of the data memory 301 on an ECC block unit basis.

In the conventional example, in order to detect and correct the errorsin the ECC block shown in FIG. 4, the following number of access timesof the data memory 301 is needed. That is, (n₁ ×n₂) times are necessaryto write the input data. (n₁ ×n₂) times are necessary to read out tocalculate the syndromes in the C₁ direction and (n₁ -k₁ -2) times arenecessary per maximum lines to write to correct the data. In the C₂direction as well, (n₁ ×n₂) times are similarly necessary to calculatethe syndromes, (n₂ -k₂ -2) times per maximum lines are necessary tocorrect the data, and n₁ ×n₂) times are necessary to read out the outputdata. Thus, it is necessary to execute the accessing operations of total4(n₁ ×n₂)+α (α denotes the number of data to be corrected) times.

As mentioned above, according to the conventional construction, thenumber of access times of the memory is large. On the other hand,in.realization of the high operating speed (cycle time) of the memory,since it is limited, the processing time of the error detectioncorrection unit is long. In the case where the high operating speed isrequired, it is necessary to construct the circuits in parallel and tosuppress the correcting capability or the like. Such a method causes thecorrecting capability to deteriorate and increases the circuit scale anda large problem occurs. Further, although the above conventional examplehas been described with respect to the case of processing the data towhich the double encoded error correction code was added, in the case ofexecuting the processes corresponding to the double encoding or more,the number of access times of the memory increases in proportion tothem. Therefore, it is necessary to further increase the hardware scaleof the processing unit.

SUMMARY OF THE INVENTION

In consideration of the above points, it is an object of the inventionto provide a method of executing the error correction in a short time.

Another object of the invention is to provide an error correcting methodor apparatus which can execute the error correction in a short time andat the high accuracy.

Under such objects, according to a preferred embodiment of the presentinvention, there is disclosed an error correcting method in a decodingmethod of digital data having a two-dimensional arrangement includingerror correction check codes in both of the first and second directions,wherein in at least one of the first and second directions, values inwhich the result of the arithmetic operation for error correction wasadded to syndromes are obtained, and the error correction is againexecuted on the basis of those value.

Still another object of the invention is to provide an error correctingapparatus having a construction suitable to execute the error correctionat a high speed.

Still another object of the invention is to provide an error correctingapparatus which can realize the high processing speed of the errorcorrection for the data to which the multiple encoded error correctioncode was added.

Under the above objects, according to a preferred embodiment of theinvention, there is disclosed an error correcting apparatus comprising:a plurality of syndrome calculating units to which input data added witha multiple encoded error correction code is supplied; a syndrome memoryto store syndromes oalculated by the plurality of syndrome calculatingunits: a data memory which is connected in parallel with the pluralityof syndrome calculating units for the input data; and a correctionprocessing unit to execute the error correction for data in the datamemory by using the syndromes stored in the syndrome memory.

The above and other objects and features of the present invention willbeccome apparent from the following detailed description and appendedclaims with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a memory construction in an embodiment ofthe present invention;

FIG. 2 is a block diagram showing a construction of an error correctingapparatus as an embodiment of the invention;

FIG. 3 is a diagram showing a construction of a product code;

FIG. 4 is a diagram showing a data block to which an error correctioncode was added; and

FIG. 5 is a block diagram showing an example of a construction of aconventional error correcting apparatus.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the first embodiment of the present invention which will be describedhereinbelow, in the decoding of digital data having a two-dimensionalarrangement having a digital data train of n₁ words including errorcorrection detection check codes of k₁ words in the first direction anda digital data train of n₂ words including error correction detectioncheck codes of k₂ words in the second direction, there is disclosed adata decoding method whereby in the case of repetitively executing theerror correction in the first direction and the error correction in thesecond direction, there is provided memory means for storing the valuesin which the arithmetic operation corresponding to the error correctingoperation which was executed in the first direction was applied tosyndromes as a result of the error correction in the first direction andthe values in which the arithmetic operation corresponding to the errorcorrecting operation which was executed in the second direction wasapplied to the syndromes as a result of the error correction in thesecond direction. However, the invention is not obviously limited tosuch a construction.

An embodiment of the invention will be described hereinbelow.

It is assumed that all of the following arithmetic operations in theembodiment relate to the arithmetic operations on the Galois field. Inthe embodiment, the code words of c₁ or c₂ are based on the Reed Solomoncode and a check. matrix H is as follows. ##EQU1## where d is a hammingdistance.

    C=(c.sub.n-1, c.sub.n-2,. . . c.sub.1, c.sub.0)

it is the reception code words such that

    C=(c.sub.n-1 +e.sub.n-1, . . . , c.sub.1 +e.sub.1, C.sub.0 +e.sub.0)

to which error patterns E

    E=(e.sub.n-1, e.sub.n-2, . . . e.sub.1, e.sub.0)

were added on the transmission path are decoded. When all of the errorpatterns are 0, C=C and all of the syndromes are set to 0. Suchsyndromes S_(j) (j=0 to d-1) are expressed by ##EQU2##

Since there are n₂ code words in the A direction, assuming that ahamming distance is set to d₁, the number of syndromes cbrresponding tothose n₂ code words is

    n.sub.2 ×(d.sub.1 -1)

On the other hand, assuming that a hamming distance is set to d₂, k₁×(d₂ -1) syndromes exist in the B direction.

All of the syndromes are stored into memories A and B shown by S(c₁) andS(c₂) in FIG. 1. In the embodiment, in each error correcting process,after the error correction in step (4) was executed,

    e.sub.x ·α.sup.xj

in consideration of the syndrome number j is added to the error patterne_(x) and error position α^(x) which were estimated for the relevantsyndrome.

That is, assuming that the new syndrome is set to S_(j) '.

    S.sub.j '=S.sub.j +e.sub.x α.sup.xj

The new syndrome S_(j) ' is written into the memory A or B and is usedas a basic syndrome in the next, that is, the second and subsequentrepetitive error correcting operations.

Due to this, in the second (t=2) and subsequent repetitive errorcorrecting operations, there is no need to execute the arithmeticoperation of each syndrome. The content of the memory S(c₁) or S(c₂)coincides with the value of the syndrome at each time point.

Therefore, the time which is necessary for the processes of repetitive ttimes is calculated in a manner similar to the above and becomes asfollows.

    {(n.sub.1 +n.sub.1)n.sub.2 +(n.sub.2 n.sub.2)k.sub.1 }+{n.sub.1 n.sub.2 +n.sub.2 k.sub.1 }(t-1) =(t+1)(n.sub.1 n.sub.2 +n.sub.2 k.sub.1)(2)

Thus, it will be understood that the processing time is reduced by onlythe time of

    (t-1)(n.sub.1 n.sub.2 +n.sub.2 k.sub.1)

as compared with the processing time shown in the equation (1) in theconventional example.

Although the above embodiment has been described with respect to thecalculation of the processing time, for instance, in the case ofexecuting the processes in steps 1 and steps 2 to 4 by the pipelineprocesses or the like, the processing time is merely slightly reduced;however, the circuits for such pipeline processes can be remarkablydecreased. On the other hand, in the case of executing only steps 2 to 4by the pipeline processes, assuming that the circuit scale is the same,the processing time can be obviously reduced into about half the time.

As described above, according to the method of the embodiment, a datadecoding method which can extremely reduce the processing time can beprovided.

A construction of an error correcting apparatus in another embodiment ofthe invention will now be described.

FIG. 2 is a diagram showing a construction of an error correctingapparatus for executing one correction decoding of the double encodedReed Solomon code as shown in FIG. 4. Data to which the double encodedReed Solomon code was added is supplied to an input terminal 114 througha transmission path. The input data is written into a data memory 112 ona data block unit basis of eight bits. The data memory 112 has acapacity which can store the data in which the error correction codeswere eliminated from data to be arithmetically operated in a syndromecalculating unit, which will be explained hereinlater. Simultaneouslywith the writing of the input data into the data memory 112, syndromesof C₁ and C₂ are simultaneously calculated in syndrome calculating units101 and 105. The syndrome calculating unit 101 on the C₁ side comprises:adders 103, 103', and 103"; one-data delays 102, 102', and 102"; andmultipliers 104 and 104'. Assuming that reception data is set to W_(i)and the root of the generating polynomial is set to α^(m), syndromes S₀, S₁, and S₂ can be calculated by the following equations (1) to (3).##EQU3##

On the other hand, in the syndrome calculating unit 105 on the C₂ side,one-line delays 108, 108', and 108" to execute the arithmetic operationsin the vertical direction are added to one-data delays 106, 106', and106". The calculating unit 105 calculates syndromes by the arithmeticoperations of the above equations (1) to (3) in a manner similar to thecase of C₁. Reference numerals 107, 107', and 107" denote adders and 109and 109' indicate multipliers.

The calculated syndromes are sequentially written into a syndrome memory110. The syndromes are rewritten by the syndrome memory 110 as will beexplained hereinlater, so that the parallel processes can beaccomplished. The error correcting operation will now be describedhereinbelow. At a time point when the error correcting operation isexecuted, the writing of the input data into the data memory 112 and thewriting of the syndromes of C₁ and C₂ into the syndrome memory 110 havealready been completed. The correcting operation is executed by a seriesof processes such that an error detection correction processing unit 111reads out the syndromes from the syndrome memory 110 and calculates theerror position and size and rewrites the erroneous data in the inputdata in the data memory 112 on the basis of the result of the errorposition and size calculated. Such processes are sequentially executedwith respect to C₁ and C₂. However, since the data in the data memory112 is rewritten by the correcting operation on the C₁ side which isfirst executed, the values of the syndromes on the C₂ side of therewritten data differ. Therefore, in a manner similar to FIG. 1described, upon completion of the correcting operation on the C side,the product of the size of error of the data corrected by C₁ and theerror position on the C₂ side of the data is added to the originalsyndromes on the C₂ side of the data, thereby rewriting the syndromes inthe syndrome memory 110. Due to this, even if the calculations of thesyndromes of C₁ and C.sub. 2 are simultaneously executed, the accurateerror correcting operation can be executed. At the time point when thecorrecting processes of C₁ and C₂ was finished, data is output from thedata memory 112 through an output terminal 115. All of timing signalswhich are used in the apparatus in the embodiment are generated by atiming controller 113.

According to the above embodiment, since the hardware is constructed soas to calculate the (n-k-2) syndromes simultaneously with the writing ofthe input data, the similar processes can be executed for the time whichis about 1/(n-k-2) shorter than that in the conventional apparatus.

According to the construction of the above embodiment, syndromes of aplurality of codes can be simultaneously calculated by a plurality ofsyndrome calculating units and the data accessing operations to the datamemory can also be simultaneously executed. This is because thesyndromes are rewritten in the syndrome memory. That is, even if thecalculations of the syndromes of the multiple codes are simultaneouslyexecuted, the error correcting processes can be correctly executed inthe syndrome memory on the basis of the rewritten syndromes. Thus, thenumber of access times to the data memory remarkably decreases and thehigh error correction processing speed can be realized.

The above embodiment has been described with respect to the example ofthe double encoding. However, even in the case of handling the datawhich was subjected to the triple or more encoding, by similarlyarranging a plurality of syndrome calculating units in parallel, theerror correcting processes can be executed without increasing the numberof access times of the memory.

As described above, according to the error correcting apparatus of theembodiment, it is possible to realize the high error correctionprocessing speed for the data to which the multiple encoded errorcorrection code was added without increasing the hardware scale.

What is claimed is:
 1. A method of decoding digital data including errorcorrection check codes in both of first and second directions when datais two-dimensionally arranged, comprising the steps of:obtaining valuesin which the result of an arithmetic operation for error correction inat least one of said first and second directions is added to syndromesin the other direction; and detecting and correcting an error positionwithin said digital data again on the basis of said values.
 2. A methodaccording to claim 1, wherein an erroneous digital data isc_(n-1)+e_(n-1), . . . , C₁ +e₁, and C₀ +e₀, (C_(n-1), . . . , C₁, and C₀ arecode words; and e_(n-1), . . . , e₁, and e₀ are error patterns on atransmission path); and wherein said syndromes S_(j) are expressed by##EQU4## (i, j and n are integers and α is a constant).
 3. A methodaccording to claim 1, further comprising the step of:repeating the stepof obtaining the added value and the step of again detecting andcorrecting the error position in accordance with this sequence.
 4. Amethod according to claim 1, wherein said result of the arithmeticoperation is e_(x) ·α^(xj') in consideration of the syndrome number j tothe estimated error pattern e_(x) and error position α^(x) for saidsyndromes.
 5. A method according to claim 1, wherein said digital datais Reed Solomon code.
 6. An error correcting apparatus comprising:(a) aplurality of syndrome calculating units to which input data added with amultiple encoded error correction code is supplied; (b) a data memorywhich is connected in parallel with said plurality of syndromecalculating units for said input data; (c) a syndrome memory to storesyndromes calculated by said plurality of syndrome calculating units;and (d) an error correction processing unit to execute error correctionof the data in said data memory by using the syndromes stored in saidsyndrome memory.
 7. An apparatus according to claim 6, wherein saidsyndrome calculating unit includes:(a) a delay to delay the input data;and (b) a multiplier to multiply the data delayed by said delay and apredetermined coefficient.
 8. An apparatus according to claim 6, whereinsaid data memory has a capacity enough to store the data in which anerror correction code is eliminated from the data which is calculated bysaid syndrome calculating unit.
 9. An apparatus according to claim 6,wherien said syndrome memory is constructed as a memory for exclusiveuse.
 10. An apparatus according to claim 6, wherein said errorcorrection processing unit calculates error position and size by usingsaid syndromes.
 11. An error correcting apparatus comprising:(a) aplurality of syndrome calculating units to which input data added with amultiple encoded error correction code is supplied; (b) memory means forstoring said input data, wherein the input data is written substantiallysimultaneously with the calculating by said plurality of syndromecalculating units; and (c) a processing unit to calculate error positionand size of said input data stored in said memory means by using aplurality of syndromes calculated by said plurality of syndromecalculating units.
 12. An apparatus according to claim 11, wherein saidprocessing unit corrects the input data stored in said memory means onthe basis of the calculated error position and size.
 13. An apparatusaccording to claim 11, wherein said plurality of syndrome calculatingunits are connected in parallel.
 14. An apparatus according to claim 11,wherein the number of said syndrome calculating units corresponds to thenumber of syndromes to be calculated.